This invention relates to determining suitable routing for connecting xe2x80x9cwiresxe2x80x9d in integrated circuits.
Integrated circuits are normally designed as a plurality of functional circuit cells, including, for example, memory cells, buffer cells, analog circuit cells, logic cells, etc. In an integrated circuit, connections between different cells are provided by xe2x80x9cwiresxe2x80x9d which are conductive paths which may extend through or past one or more cells to provide connections in the integrated circuit on a more global scale. The wires are normally implemented as tracks in one or more layers of metallisation on the semiconductor substrate.
Dedicated routing software tools are available for routing the wires on the integrated circuit. Once the topography of the individual cells has been designed, the router operates to determine the paths across the integrated circuit of the connecting wires on a global scale.
Problems can occur if wires are routed over or adjacent to certain areas of sensitive cells, such as analog cells or memory cells. Interference can occur between the circuit of the cell and the signals in the wire, causing incorrect circuit performance.
With conventional routers, it is possible to xe2x80x9cblock outxe2x80x9d certain sensitive cells from the router, such that the router will not route any wires over the blocked cells. This can avoid the interference problems mentioned above, but it does result in reduced availability for wire routes within the integrated circuit. This is referred to as low cell xe2x80x9cporosityxe2x80x9d. If a designer is very cautious in the design of an integrated circuit, he may block out all of the potentially sensitive cells, which can lead to the router operating very slowly, or even having insufficient routing room to provide paths for all of the necessary wires. If the router fails, the designer will either have to un-block some of the cells, or he will have to define the wire routes manually, which is a very difficult and labour intensive task.
As die sizes become larger, and the number of mixed signal and sensitive cell devices in integrated circuits continues to increase, the problem of global signal routing over such cells and components is becoming more apparent.
The present invention has been devised bearing the above problems in mind.
In contrast to the prior art, one aspect of the present invention is to define at least one circuit cell having at least one wire route and/or at least one possible wire route defined as part of the cell.
The invention enables advantage to be taken of the fact that, even for sensitive cells, there may be one or more possible wire routes through the cell without the wire coming close to sensitive areas circuitry of the cell. By building such wire routes, or possible wire routes, in to the cell at the cell-design level, it is not necessary to block out the entire cell to the routing software. Instead, the routing software can access the allowable routes through the cell as part of the overall routing design.
Furthermore, the designer can determine the number of wire routes which are permissible through the cell. In the prior art technique, a cell is either transparent in that any number of wire routes can be placed through the cell, or it is blocked out, meaning that no wire routes are allowed. With the new technique, the cell designer can control the number of wire routes available to the router software.
A further advantage is that the cell designer can design suitable routes through the cell for differential signal wires, such that each wire is subject to the same interference. Alternatively, the effect of a signal within a wire, on differential signals within the cell, can be predicted and utilised to provide wire routes through sensitive areas of the cell.